The present invention relates to an analog/digital (hereinafter called “A/D”) converter circuit, and particularly to a multi-input A/D converter circuit.
FIG. 2 is a schematic configuration diagram of a conventional A/D converter circuit.
The present A/D converter circuit performs processing on a multi-input and has input terminals 11i respectively inputted with analog input signals INi (where i=1 to 256). Capacitors 13i and buffers 14i are respectively connected to the input terminals 11i via switches 12i. The capacitors 13i respectively hold the input signals INi sampled by the switches 12i and have other ends connected to a ground potential GND. The buffers 14i are used to output the voltages (input signals INi) held in the capacitors 13i at low impedance without changing the voltages. The buffers 14i are constituted of voltage-follower connected operational amplifiers or the like. A node NA is connected to the output sides of the buffers 14i via switches 15i. An A/D converter (hereinafter called “ADC”) 16 is connected to the node NA. A digital output signal OUT is outputted from the ADC 16.
In the A/D converter circuit, all the switches 121 through 12256 are turned on during a sampling period, and the input signals IN1 through IN256 are applied to their corresponding capacitors 131 through 13256. At this time, the switches 151 through 15256 are all off. When the sampling period is ended, all the switches 121 through 12256 are turned off and hence the input signals IN1 through IN256 are retained in their corresponding capacitors 131 through 13256, so that a hold period is reached.
When the hold period is reached, the switch 151 is first turned on so that the same voltage as the input signal IN1 held in the capacitor 131 is outputted from the buffer 141 to the node NA through the switch 151. Then, the analog voltage of the node NA is converted into a digital signal by the ADC 16, which in turn is outputted as an output signal OUT.
Next, the switch 151 is turned off and the switch 152 is turned on. Then, the same voltage as the input signal IN2 retained in the capacitor 132 is outputted from the buffer 142 to the node NA through the switch 152 and converted into a digital signal by the ADC 16, which in turn is outputted as an output signal OUT. Thus, the output voltages of the buffers 141 through 14256 are sequentially switched by the switches 151 through 15256 and converted into their corresponding digital signals in turn by the ADC 16.
The above prior refers to a patent document 1 (Japanese Unexamined Patent Publication No. Hei 7(1995)-38439).
The A/D converter circuit involves, however, the following problems.
That is, the buffers 141 through 14256 are provided for impedance transformation and circuit separation. The selector switches 151 through 15256 provided on the output sides of the buffers 141 through 14256 are sequentially turned on/off to supply the output voltages of the buffers 141 through 14256 to the ADC 16 in turn, after which they are converted into their corresponding digital values. Since there is a need to prepare the buffers 14 by the same number as the input signals IN, a layout area occupied by theses buffers 14 and current consumption thereof increase as the number of the input signals increases. Thus, it is difficult to provide a large number of high-capacity buffers. Only buffers small in capacity are provided and hence drive capacity is restricted. Therefore, a problem arises in that when each of the switches 15 is turned on and the output voltage of each buffer 14 is outputted to the node NA, a response time required up to the stabilization of each voltage of the node NA becomes longer.
Assuming that, for example, a load capacitance C connected to the node NA is 5 pF, an output current I of one buffer 14 is 5 μA and a response voltage V of the buffer 14 is 5V, an electrical charge Q charged to the load capacitance is placed in a relationship of Q=CV=IT (where T: time during which the output current I flows). Therefore, the time becomes T=5 pF×5V/5 μA=5 μs. Assuming that the response time required to stabilize the voltage of the node NA is 4 T, the response time becomes 20 μs.
Assuming that a sampling speed is set to 10 MHz or so where the ADC 16 is of a normal successive approximation type, the time required to convert data becomes 1 μs or so. Therefore, the sum of time intervals required to A/D-convert the input signals IN1 through IN256 results in about 5.4 ms (256×21 μs). Even though the high-speed ADC 16 having the sampling speed of 40 MHz is used, the sum of the A/D conversion times almost remains unchanged because the response times of the buffers 14 are dominant over the A/D conversion times.
As a method for shortening the A/D conversion time, there is known one wherein a plurality of ADCs are prepared to perform AD conversions in parallel. This has however a fear that a layout area and current consumption increase.